1. Field of the Invention
The present invention relates to a semiconductor memory device for accessing a memory cell in a memory array belonging to one of a plurality of banks into which a plurality of memory arrays are classified, and a method for producing such a semiconductor memory device.
2. Description of the Related Art
A conventional semiconductor device is disclosed in, for example, Japanese Laid-Open Publication No. 6-76567. In the semiconductor memory device disclosed in the above-mentioned publication, memory arrays are classified into two or four banks in accordance with whether the data input and output is performed at a unit of 8 bits (.times.8 structure) or 4 bits (.times.4 structure).
The number of banks is determined in accordance with the number of a series of pieces of data wrap length accessible by one address input in lieu of being set in accordance with the number of bits included in one piece of data.
In a structure where the memory arrays are classified into a plurality of banks, data transfer rate is improved by performing an interleave operation, in which banks are accessed alternately.
FIG. 6 is a block diagram of a device for switching the number of banks, which is also disclosed in Japanese Laid-Open Publication No. 6-76567.
In FIG. 6, a pad PD is connected to a power supply potential Vcc or a ground potential Vss by wire bonding. A pad potential detection circuit 100 detects a potential of the pad PD and outputs a "high" signal (high level) or "low" signal (low level). In response to the potential of the signal sent from the pad potential detection circuit 100, a bank selection circuit 102 performs a 2-bit or 1-bit decoding operation, thereby generating a bank selection signal.
The bank selection circuit 102 receives two-bit selection address signals A11 and A10. When the output signal from the pad potential detection circuit 100 represents a .times.4 structure, the bank selection circuit 102 decodes the two-bit signals A11 and A10, and one of four-bit bank selection signals BA0 through BA3 is set to a selecting state. In other words, the bank selection circuit 102 generates the four-bit bank selection signals BA0 through BA3 in order to set four banks. By the bank selection signals, the banks are sequentially selected and thus activated.
When the output signal from the pad potential detection circuit 100 represents a .times.8 structure, the bank selection circuit 102 invalidates one of the two-bit address signals A10 and generates two-bit bank selection signals B0 and B1 in accordance with the other signal A11. In other words, the bank selection circuit 102 generates the two-bit bank selection signals B0 and B1 in order to set two banks. By the bank selection signals, the banks are sequentially selected and thus activated.
The system shown in FIG. 6 is applicable to a structure in which the number of banks is determined in accordance with the wrap length. In such a structure, the pad PD is connected to the power supply potential Vcc or the ground potential Vss depending on whether the wrap length is 8 or 4. The pad potential detection circuit 100 is used as a wrap length setting circuit, and the bank selection circuit 102 generates a bank selection signal.
However, in the above-described structure, the potential of the pad PD is determined by wire bonding, which determines the number of the banks. Accordingly, as the number of banks to be set increases, the number of required pads also increases. For example, when the number of banks is set to be 2, only one pad is required. When the number of banks is set to be four, two pads are required.
In this manner, the number of required pads increases along with the number of banks to be set, which results in an increase in the chip area required for the pads.